Various methods and configurations of electronic packages have been previously detailed. For instance, U.S. Pat. Nos. 7,790,500, 7,799,611, 7,129,116, 6,812,552, each entitled “Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging” and filed Oct. 24, 2007, Oct. 26, 2006, Aug. 10, 2004 and Apr. 29, 2002, respectively, are directed to near-chip scale packages. The disclosures of U.S. Pat. Nos. 7,790,500, 7,799,611, 7,129,116, 6,812,552 are incorporated by reference herein in their entirety.
In making electronic packages that use lead frames, there are several process steps that subject the lead frames to mechanical and thermal stresses. The finer geometries of current lead frames and the ever-increasing integration of circuits on semiconductor chips have resulted in processing that places even greater stress on the lead frames. Finely configured lead frames often resemble very delicate embroidery, or stencil-like metal structures that tend to bend, break, disfigure and deform easily. Many conventional lead frames are used in the industry to create a variety of chip packages, including wire bonded and flip-chip (FC) packages.
Conventional lead frames often lack structural rigidity. The finger-like portions of lead frames can be quite flimsy and difficult to hold in position. This leads to handling flaws, damage and distortion in assembly processes and complicated wire bonding situations. Consequently, bond parameters have to be optimized to compensate for lead frame bouncing during the bonding process. A failure to optimize the bonding parameters to compensate for the mechanical instability of the lead frame can result in poor bond adhesion, and hence poor quality and poor reliability of the bond.
The large metal plate portions of a typical lead frame extend from a central portion, known as the chip receiving area, also known as a chip-pad. The chip is usually attached to the receiving area with the backside down, and the side of the chip with electronically conductive circuit traces positioned face up with terminals located peripherally on the perimeter of the chip, or over the surface of the chip in the form of an array. The receiving area typically has dimensions of about 5 mm×5 mm, and the leads extending outwardly from the chip-pad area have typical dimensions of about 10 mm long×1 mm wide×0.2 mm thick. The lead frame is typically held down by a vacuum chuck and mechanical clamps. The chuck and clamps must be refitted for lead frames of different sizes and shapes.
Quad flat no-lead (QFN) packages, whose lead surfaces are often electronically connected to printed circuit boards via solder balls, may have these connections severed when subjected to rigorous stress in certain applications, such as in automobiles. Furthermore, inspection and verification of the quality of such connections may be difficult to verify visually and without physically stressing the connections.
The subject matter of the present disclosure is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.